1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, it relates to a semiconductor memory device having an improved circuit for temporarily equalizing the potential of the complementary signal lines when changing an address signal.
2. Description of the Related Art
A semiconductor memory device having a plurality of static type memory cells, especially non-synchronous type memory cells, comprises at least a pair of bit lines, a word line, a pair of load transistors each connected to a bit line, and a static type memory cell having a plurality of transistors and two load resistors.
In this type of memory cell, the writing and reading of information to and from the memory cell is performed by changing the potential of bit lines having a complementary relationship, i.e., one bit line has a high potential and the other bit line has a low potential.
Therefore, access time to the memory cell is determined mainly by the speed of the change in potential of the bit lines.
Japanese Unexaminated Patent Publication (Kokai) No. 57-150188, for example, discloses a technique for reducing the access time to the memory cell by providing a circuit for temporarily equalizing the potential of the complementary bit lines when changing the address signal.
Such a circuit, however, does not sufficiently reduce the access time to the memory cell, because a transistor used for equalizing does not turn ON completely at the time that the changing of the potential ends.
This problem will be explained in detail hereinafter.